As semiconductor technology advances, circuit elements and interconnections on wafers or silicon substrates become increasingly more dense. As a result of the continuing trend toward higher device densities, parasitic interdevice currents are increasingly problematic. In order to prevent unwanted interactions between circuit elements, insulator-filled gaps, or trenches, located between active circuit devices and metallized interconnect layers are provided to physically and electrically isolate the elements and conductive lines. However, as circuit densities continue to increase, the widths of these gaps decrease, thereby increasing gap aspect ratios, typically defined as the gap depth divided by the gap width. As the gaps become narrower, parasitic capacitance increases, and filling the gaps with insulating material becomes more difficult. This can lead to unwanted voids and discontinuities in the insulating, or gap-fill, material.
For example, in metal-oxide-semiconductor (“MOS”) technology, it is necessary to provide an isolation structure that prevents parasitic channel formation between adjacent devices, such devices being primarily NMOS and PMOS transistors or CMOS circuits. Trench isolation technology has been developed in part to satisfy such insulation needs. Refilled trench structures essentially comprise a recess formed in the silicon substrate that is refilled with a dielectric insulating material. Such structures are fabricated by first forming submicron-sized trenches in the silicon substrate, usually by a dry anisotropic etching process. The resulting trenches typically display a steep side-wall profile. The trenches are subsequently refilled with a dielectric, such as silicon dioxide, typically by a chemical vapor deposition (“CVD”) technique. They are then planarized by an etchback process so that the dielectric remains only in the gap, its top surface level with that of the silicon substrate. The resulting filled-trench structure functions as a device isolator having excellent planarity and potentially high aspect ratio beneficial for device isolation. Refilled trench isolation can take a variety of forms depending upon the specific application; they are generally categorized in terms of the trench dimensions: shallow trenches (<1 μm), moderate depth trenches (1 μm to 3 μm), and deep, narrow trenches (>3 μm deep, <2 μm wide). Shallow Trench Isolation (STI) is used primarily for isolating devices of the same type in increasingly dense MOS circuits. STI provides a high degree of surface planarity.
Similar isolation techniques are used to separate closely spaced circuit elements that have been formed on or above a semiconductor substrate during integrated circuit fabrication. The circuit elements may be active devices or conductors, and are isolated from each other by refilled “gaps”.
The basic trench, or gap, isolation process is, however, subject to drawbacks, one of these being void formation in the gap during dielectric gap fill. Such voids are formed when the gap-filling dielectric material forms a constriction near the top of the gap, preventing deposition of the material into the gap interior. Such voids compromise device isolation, as well as the overall structural integrity. Unfortunately, preventing void formation during gap fill often places minimum size constraints on the gaps themselves, which may compromise device packing density or device isolation.
Silicon dioxide is formed by conventional CVD techniques by mixing a gaseous oxidizer (e.g., N2O), silane (SiH4) and inert gases, such as argon, and energizing the mixture in a reactor so that the oxygen and silane react to form silicon dioxide on a wafer substrate. Plasma-enhanced chemical vapor deposition (“PECVD”) processes are used to fill gaps with silicon oxide material. In PECVD processes, a plasma of ionized gas is formed in the CVD plasma reactor. The plasma energizes the reactants, enabling formation of the desired silicon dioxide at lower temperatures than would be possible by adding only heat to the reactor system. In a typical plasma-enhanced CVD (“PECVD”) process, the plasma is a low pressure reactant gas discharge that is developed in a radio-frequency (“RF”) field. The plasma is an electrically neutral ionized gas in which there are equal number densities of electrons and ions. At the relatively low pressures used in PECVD, the electron energies can be quite high relative to heavy particle energies. The high electron energy increases the density of dissociated reactants within the plasma available for reaction and deposition at the substrate surface. The enhanced supply of reactive free radicals in the PECVD reactor enables the deposition of dense, good quality films at lower temperatures (e.g., 400° C.) and at faster deposition rates (30 nm/min to 40 nm/min) than typically achieved using only thermally-activated CVD processes (10 nm/min to 20 nm/min). Nevertheless, the gap-fill capabilities of PECVD techniques do not extend beyond aspect ratios of about 2.
Design feature widths of integrated circuit devices are currently approaching 0.1 μm, or 100 nm. To achieve corresponding overall circuit density, gap dimensions of approximately 25 nm to 300 nm gap width range and 100 nm to 1000 nm gap depth range are desired, having a corresponding range of aspect ratios of 2 to 6. Furthermore, because the gap is so thin, the insulating gap material should have a dielectric constant of 3.3 or less. A gap opening of 500 nm or less is too small for depositing material using conventional CVD and PECVD methods. Also, as the deposition of gap-filling material proceeds, the gap opening becomes smaller, making it more difficult to fill and creating the risk of void formation.
Currently, high density plasma (“HDP”) CVD is used to fill high aspect ratio gaps. In an HDP-CVD process, RF bias is applied to a wafer substrate in a vacuum chamber. As a result, the flux of deposition precursors is perpendicular the wafer, and film growth tends to occur perpendicularly to the bottom of the feature, rather than on feature sidewalls. Thus, HDP-CVD is not an entirely diffusion-based (isotropic) process. Typical HDP-CVD processes use a gas mixture containing oxygen, silane, and inert gases, such as argon, to achieve simultaneous dielectric deposition and sputtering. Some of the gas molecules, particularly argon, are ionized in the plasma and accelerate toward the wafer surface when the RF bias is applied to the substrate. Material is thereby sputtered when the ions strike the surface.
HDP-CVD processes operate at a pressure regime several (two to three) orders of magnitude lower than that of PECVD processes. Also, using HDP-CVD, it is usually possible to deposit silicon oxide films at lower temperatures (e.g., 150° C. to 250° C.) than in a PECVD process. In an HDP reactor, power is coupled inductively to the plasma, resulting in higher plasma density. Consequently, in an HDP reactor, because of the pressure and plasma characteristics, species impinging on the depositing film surface are much more energetic than in a PECVD reactor, such that gas-solid collisions typically result in sputtering of the deposited film. In an HDP-CVD deposition process, the sputter component is typically between 10% and 20% of the net deposition rate. Another characteristic of HDP-CVD deposition is that increased bias power applied to the wafer results in an increased in situ sputter component, thereby decreasing the deposition rate.
In a HDP-CVD process, dielectric material deposited on the wafer surface is simultaneously sputter-etched, thereby helping to keep gaps open during the deposition process, which allows higher aspect ratio gaps to be filled.
Nevertheless, a problem often encountered in HDP-CVD processes is the deposition of more material on the upper region of a gap sidewall than on the lower region of the gap. High aspect ratio gaps often exhibit reentrant features, which make filling even more difficult. The most problematic reentrant feature is a narrowing at the top of the gap. Thus, the deposited dielectric material slopes inward near the top of the gap. For a given AR, this increases the ratio of gap volume to gap access area seen by the precursor species during deposition. Hence, voids and seams become even more likely. The formation of cusps in the upper region or at the entrance of a gap, also called “overhang”, typically results from the non-directional deposition reactions of neutral species in the plasma reactor and from sputtering/re-deposition processes. The directional aspect of deposition processes produces high momentum charge species that sputter away bottom fill. The sputtered material tends to re-deposit on the side walls. Thus, in conventional HDP-CVD processes, cusp formation at the entry region of high aspect ratio gaps to be filled cannot be totally eliminated because sputtering and re-deposition reactions are inherent to the physics and chemistry of a conventional HDP-CVD process.
FIG. 1 depicts schematically a cross-sectional view 100 of a high aspect ratio gap 102 partially filled with dielectric material 104 using a conventional HDP-CVD process. As depicted in FIG. 1, the conventional HDP-CVD process provided bottom filling of the bottom 106 of gap 102 in substrate 107. Sputtered dielectric material, however, re-deposited on the side walls 108 of gap 102, particularly at gap opening 110. As a result, overhanging dielectric material 112 prematurely closed gap opening 110 before gap 102 was completely filled, resulting in formation of void 114. The dielectric material deposited in 102 also includes a weak spot 116. Weak spots form as a result of increased ratio of gap volume to gap access area as the amount of undesired overhang increases during bottom filling. Weak spots typically lead to formation of voids and seams. Also, compared to the thickness of deposited dielectric material filling of the bottom of 102, the amount of dielectric material 104 deposited in the field areas 120 of substrate 107 is excessive.
Thus, there is a need for a method of depositing gap-filling dielectric material for filling an insulator gap, or a trench, having an aspect ratio of 2 or greater.